Selective calling system



May 21, 1968 R. I SHARMA 3,384,873

SELECTIVE CALLING SYSTEM Filed Jan. 22, 1965 6 Sheets-Sheet 1 FIG 5MESSAGE SOURCE v BINARY SYSTEM MODULATOR IIIIIE b I SOURCE q IOSCILLATOR I--- 250 I F T //2 MEANS FOR /34 MEANS FOR 'IIIII I {I -Ki--II=-- [MOMENTARILY b f MOMENTARILY T T F F IG la /26 I27 SIIIIIII FT PI l 5'2 '5 De I /30 FEEDBACK I S I FJ AI i I OUTPUT OF INITIAL SHIFT ROWSETTING REGISTER I00 I I0I IIOOIOI 2 mo lllOOlO 3 0m oIIIooI 4 I00IoIIIoo 5 no oIoIIIo F 2 6 III ooIoIII 7 OH IOOlOll iia lOl I IOOIOOFIRST PULSE GENERATED AT OUTPUT INVENTOR.

ROSHAN LAL SHARMA 5 ATTORNEYS May 21, 1968 Filed Jan. 22, 1965 R. L.SHARMA SELECTIVE CALLING SYSTEM 6 Sheets-Sheet 3 (A) /44 /a/ 62 SAMPLINGIf II II PULSES I I I I I I I) I: I I II f V II I f I g I 1 II no" "In(B) x H A I I REcEIvEo I I I I I DATA I I I l Um I t I; l III L w; 1/63I I I SAMPLED f I I ff RECEIVED I I I I 1 DATA I l I i I\ I I I I I If.I I I I I I I I I /68 D) I I46: I m lfih SHIFT I I PULSES I I I I I I II I I I66 I l I l 3 m (E) I I I I 1%, I I I I I HII IT-I I I I EI I:

I I i E i I ,1 /64 11,: I I

sTATIoN I TRANSMITTER REcEIvER A V I Y TRANSMITTER RECEIVER TRANSMITTERREcEIvER STATION 2 /2/ 22 sTATIoN 3 INVENTOR.

ROSHAN LAL SHARMA AT TORNEYS y 21, 1968 R. 1.. SHARMA 3,384,873

SELECTIVE CALLING SYSTEM Filed Jan. 22, 1965 6 Sheets-Sheet 5 ,0 I80RECEIVER 7 DEMODULATOR 5 9 J,

RECEIVER SYNCRONIZING SOURCE FREQUENCY F| /83 -$H|FT SAMPLES J C SHIFTTIMING INPUT HlgH RATE "@D souRcE v (RATE I4F) COUNT OF 7- RESET TO 0L50 ON F| SAMPLING k COUNTER 33 2' v O? 30 v DELAY MEANS (GREATER OUTPUTCOUNTS |-7 La/ THAN F| 48 50' PULSE F 7 -1{ DURATION) /56 i orfi rsA raNe \5/ 4 1 49 1 COUNT OF 6 BISTABLE I DEVICE T J SAMPLING: PULSE ROSHANLAL SHARMA Wm 6/ ATTORNEYS United States Patent M 3,384,873 SELECTIVECALLING SYSTEM Reslran Lal Shanna, Tustin, Califi, assignor to CollinsRadio Company, Cedar Rapids, Iowa, a corporation of Iowa Filed Jan. 22,1965, Ser. No. 427,384 5 Claims. (Cl. 349-146.1)

ABSTRACT 0F THE DISCLOSURE A selective calling system including meansfor generating an address recognition code followed by an address code,with both of said codes being of the cyclical, or redundant, type. Atthe receiver, means are provided to receive and identify the addressrecognition code and then to energize an address generating circuit atthe receiver which functions to generate the address unique to thatreceiver. The receiver also receives the transmitted address code and inresponse to the address recognition code functions to compare theaddress code generated at the receiver with the received address code todetermine the degree of coincidence. If coincidence is sufificientlyhigh the address is presumed correct.

This invention relates generally to selective calling systems and moreparticularly, to selective calling systems employing cyclical groupcodes rather than repetitive type addressing codes.

In cases where more than two stations or persons are involved in acommunication network some form of switching and addressing is needed toobtain communication between selected stations. In other words, a givenstation acting as a transmitter may wish to communicate with one of twoor more other stations acting, at that time, as receivers. It isnecessary to have some addressing means whereby the transmitter cancommunicate solely with the desired receiver. Such addressing ordinarilyrequires some redundancy, that is, additional transmitted digitalinformation, to enable the desired receiver to be identified as thecalled receiver. Redundancy may be termed as additional informationrequired to demultiplex different stations using the same networkfacility. Redundancy has another use which involves protecting digitalcommunication link against the randomly occurring errors which exists inevery known communication system.

In most conventional addressing schemes the information or the messagesare surrounded, or preceded by some form of repeated address, of thestation to which the message is sent, and followed by a repeated stopcode. For example, a receiving station may be designated by an addressXYZ, The message may be preceded by three transmissions of XYZ. Thereceiving station can make a majority decision as to the addressedstation by observing if two out of the three transmitted addresses werethe same. In doing so, the receiving station can compare the receivedaddresses in three different manners.

Firstly, the receiver can compare the respective address symbols aswhole units, so that at least two of the three addresses must be theaddress XYZ.

Secondly, the receiver may compare the received address as addresssymbols. As example, assume the addresses received were distorted due tonoise so that the received symbols were as follows:

By comparing the specific symbols of the received address, the receiveris able to make a majority decision of 3,384,873 Patented May 21, 1968XY Z since each of the symbols, X, Y, and Z occur at least twice in itsproper position in the received codes.

The third method by which the receiver may identify the received addressis to compare the binary digits of the received address codes. Ifetficiency is defined as a probability of complete recognition of theaddress, it can be shown that the efficiency for the third mentionedcomparison technique is better than the other two and that the second isbetter than the first.

Thus, in the present state of the art, a binary digit comparisontechnique is the most eflicient. It can be used more efiiciently withrepetitions of a selective calling code than any other known system.There are certain disadvantages, however, even with the binary digitcomparison technique, as outlined briefly above. Such disadvantages areas follows:

(1) There is little or no protection against loss of codesynchronization. The bits or symbols immediately surrounding the code(in a series type transmission) might be taken as a part of the code,resulting in confusion or a breakdown of the system.

(2) The selection calling identification address code may not possess anoptimum group relationship In other words, some codes may be moresimilar to each other than other codes. Such similarity in codes canresult in inefiiciency in that it takes fewer errors for any given codeto become unidentifiable from a closely related code since a few errorsin the closely related codes may also produce the same resultanterroneous code as a few errors in the first code.

An object of the present invention is an improved selective callingsystem which dispenses with repetition of an address code and insteaduses highly redundant group codes as selective calling codes.

Another object of the invention is a selective calling system using abinary bit comparison technique of a highly redundant group of binarybits without repetition.

A third object of the invention is a simplified and more efiicient typeof calling, or addressing, coding system than heretofore known.

A fourth purpose of the invention is the improvement of selectivecalling systems, generally.

In accordance with the invention there is provided a means forgenerating the redundant group code at the transmitter and another meansfor receiving and identifying the received redundant group code at thereceiver, of which there may be a plurality, each with its own uniqueaddressing code. At the transmitter the redundant group code isgenerated by a first shift register of n stages where n is at .leastthree. Although any number of stages may be employed, assume fordiscussion purposes herein, that I1 3. The first and third stages canhave outputs supplied to an exclusive OR circuit which constitutes amodulo 2 adder. -By definition, a modulo 2 adder performs the functionof producing a signal representing a binary bit 0 when pulsesrepresenting "0s are supplied to both input terminals or pulsesrepresenting ls are supplied to both input terminals thereof. When asignal representing a logic 1 is supplied to only one (either) of theinput terminals of the modulo 2 adder, and a logic 0 is supplied to theother input thereof, the output of the module 2 adder is always alogic 1. Since the output of the modulo 2 adder is supplied to the inputof the shift register, the output of the shift register will follow adefinite pattern of ls and Os as will be discussed later herein, withrepitition occurring every (2 l) output pulses, Where n is the number ofstages of the shift register. Mathematically, the above-describedconnections can be expressed by polynomials that are primitive andirreducible.

It should be noted that there are two general methods for transmittingthe redundant code. One of these methods utilizes serial transmission ofthe bits of the codes and the other method utilizes paralleltransmission of the bits of each code. In the case where transmission isin the parallel form, the receiving means will receive all the bits of agiven code simultaneously, i.e., in parallel, with the result thatrecognition of a given code is simplified with little or no possibilityof bits from adjacent codes confusing the recognition process.

In the case, however, Where transmission of the codes is in series form,the possibility of bits on either side of the address codes confusingrecognition of the address code is present. To avoid such confusion, anaddress recognition code, also consisting of 2 -1 bits, is sentimmediately preceding the address code. Such address recognition codepreferably is one of the group of codes making up the group of redundantcodes and reserved specifically for the address recognition function.All receivers are provided with means to recognize the addressrecognition code, and upon receipt thereof will be informed that thenext 2 --1 bits immediately following the address recognition codeconstitute an address code. Such address code is examined by eachreceiver to determine if it is the receiver being addressed. Only thatreceiver having such address will respond positively thereto. Thus, theaddress recognition code performs the function of maintaining codesynchronization.

As indicated above, at each receiver there is provided means forrecognizing the address recognition code. Such means may comprise asecond shift register means, all the stages of which have outputsconnected to an AND gate. The number of stages of said second shiftregister is made equal to the bit length of theaddress recognition codeand only when said shift register contains said address recognition codewill the AND gate respond thereto to provide an output pulse informingthe receiver that the next group of (Z -J) pulses will constitute anaddress code.

First counting means is also provided in the receiver to count thenumber of bits received after the address recognition code has beenrecognized. When (2 -1) bits have been received after the addressrecognition code, each receiver functions to examine said 2 -4 bits, nowstored in the shift register, to determine if such bits constitute theaddress code of that receiver.

The examination of the address code is accomplished generally asfollows. Each receiver is provided with a local redundant code generatorsimilar to that provided at the transmitter. However, the localgenerator at each receiver is unique in that it is constructed toinitiate the address code from a different setting of the stages of saidlocal code generator, and thus to generate the address of that receiveronly. At the completion of the generation of each address code thereceiver generator is reset automatically in preparation for the nextcode generation.

Generation of the local address code is effected after the address codehas been completely entered into the said second shift register and isinitiated by the output of said first counter means. The information inthe second shift register is then compared with the informationgenerated by the receiver code generator to determine if coincidenceexists. When coincidence exists between the received code, i.e., thecode stored in the second shift register, and the code generated by thelocal generator, the particular receiver in which coincidence occurssenses that it is being addressed and initiates proper circuitry for thereception of the intelligence-bearing codes which normally follow theaddress code.

Specifically, the comparison of the received data stored in the secondshift register at the receiver and the code generated by the local codegenerator is obtained by passing the information contained in saidsecond shift register, and also the code generated by the local codegroup generator, through a coincidence circuit. The code stored in thestorage shift register is immediately recirculated back into the storageshift register before the reception of the next bit.

If the degree of coincidence exceeds a predetermined threshold, gatingmeans is opened to admit to this particular receiver theintelligence-bearing information that fol lows the address (redundant)code. Only one receiver will be caused to become so receptive since eachreceiver has an address unique thereto.

After a message has been received, some means is required to indicatethe end of the message. Such function is accomplished by againtransmitting an address recognition code followed by the address code ofthe receiver being addressed. Said receiver will respond thereto todisable itself from reception of further information until theoccurrence of its next address code.

In accordance with another embodiment of the invention, means areprovided to receive address codes transmitted in parallel form. In suchan embodiment each 7-bit code, which might be a data code or an addresscode, is supplied at the receiver, in parallel, to the seven stages ofsaid second shift register. The local redundant code generator generatesits own address once after each new 7-bit code has been received; thecode in the second shift register then being compared with the locallygenerated address code.

Comparison of the received code stored in said second shift register andthe code generated by the local code generator is obtained byrecirculating the information in the said second shift register afterthe reception of each code, and at the same time generating the localaddress code from the local code generator. More specifically,comparison is made between the corresponding individual bits of thesetwo signals in coincidence circuit, and if the degree of coincidence isbeyond a predetermined threshold, gating means is opened to admit to theaddressed receiver the information following the address code. With theparallel form of transmission it is not necessary to employ an addressrecognition code.

The above and other features and objects of the invention will be morefully understood from the following detailed description thereof whenread in conjunction with the drawings in which:

FIG. 1 is a block diagram showing a means for gen- I crating theredundant code group;

FIG. 1a is a set of pulse waveforms to facilitate an understanding ofthe operation of FIG. 1;

FIG. 2 is a chart showing the redundant code groups generated forvarious initial settings of the generator of FIG. 1;

FIG. 3 is a block diagram showing a typical receiving network forsensing and evaluating a serially transmitted address received therein;

FIG. 4 is a set of waveforms showing the time relationship amongreceived data sampling pulses and circulating pulses for facilitatingunderstanding of the block diagram of FIG. 3;

FIG. 5 is a block diagram showing the general arrange ment of aplurality of stations, each station having a transmitter and receiver;

FIG. 6 is a block diagram of means for transmitting codes in parallel;and

FIG. 7 is a block diagram of means for sensing and evaluating addresscodes transmitted in parallel form.

As discussed above, the present invention functions to selectivelyaddress one of a plurality of receivers so that transmission can be madeto the selected receiver to the exclusion of the other receivers. Insome multistation systems each station has both a transmitter and areceiver, with three or more stations being employed in the overallsystem. Each station is capable of transmitting to any of the receiversof the other stations to the exclusion of all remaining receivers. Sucha system is shown in simplified manner in FIG. 5, wherein there arethree stations: 120, 121, and 122. Each of these three stations iscomprised of a transmitter and a receiver, with the transmitter of eachstation being connected to the receivers of all the remaining stations.In this circuit of FIG. 5, each transmitter is also shown as beingconnected to its own receiver. This is not an objectionable arrangementinasmuch as a transmitter ordinarily would not transmit the address codeof its own receiver. Consequently, it would not be connected to its ownreceiver.

Each of the transmitters is equipped to generate the address codes ofall receivers; said address codes being known herein as redundant groupcodes, or redundant codes. The redundant codes generated by thetransmitters are related to each other in a manner to be described indetail later. Each code consists of a series of marks and spacesarranged in a predetermined order which repeat themselves at periodicintervals. Further, each of the receivers is constructed to respond to aunique redundant code transmitted by a transmitter, i.e., each receiveris responsive to a different pattern of marks and spaces.

Referring now to FIG. 1, there is shown the block diagram of a generatorfor generating a redundant group code. The circuit of FIG. 1 consists ofa shift register 100 comprised of three stages: 101, 102, and 103. Thebits contained in the stages 101, 102, and 103 are shifted progressivelyfrom left to right by means of shift signals generated by shift signalgenerator 115 (timing pulse source) at a frequency f Such shift signalsare represented by pulses 126, 127, and 128 of FIG. 1a. As each shiftoccurs, the bits in first and third stages 101 and 103 function tosupply output pulses to input leads 105 and 106 of exclusive OR gate104, with a polarity depending upon the nature of the bits stored instages 101 and 103. If the bits stored in the first and third stages arethe same, i.e., both logic Os or both logic ls, then the output of ORgate 104 (a modulo 2 adder) is a 0. If, however, either stage 101 orstage 103 of shift register 100 contains a "1 and the other stagecontains a 0, then the output of modulo 2 adder 104 will be a 1(sometimes referred to herein as a mark). The output of modulo 2 adder104 is then supplied through lead 107 to input 108 of OR gate 110, andthence to input lead 125 of shift register 100.

Assume that the data contained in shift register 100 is as shown in FIG.1, i.e., consists of the binary code 101. When shift signal generator115 generates a pulse to shift the information contained therein forwardone stage, the 1s appearing in stages 101 and 103 produce a 0 on outputlead 107 of modulo 2 adder 104, which 0 will then be fed back to stage101. There must be sufficient delay in the system so that the shift ofthe information contained in stages 101, 102, and 103 occurs, and iscompleted, before the output of modulo 2 adder 104 is fed back intostage 101. Further, when such shifting occurs, the information containedin stage 103 is shifted out of the shift register and into modulatingmeans 111 through switch 118, where it is employed to modulate thecarrier frequency generated by oscillator 112. The modulated carrier isthen supplied to some suitable transmitting medium, such as antenna 113.The switch 118 is shown symbolically and is used to switch betweenmessage source 119 and the address generating means; which addressgenerating means constitutes most of the remainder of the circuit ofFIG. 1.

The time relation between the pulse fed back from the output of themodulo 2 adder 104 to the input of the shift register, and the shiftpulses is shown in FIG. 1a, wherein pulses 129, 130, and 131 representthe pulses fed back from the modulo 2 adder 104. It will be apparentfrom FIG. 1a that pulses 129, 130, and 131 lag shift pulses 126, 127,and 128 by a short time interval. For example, the leading edge of pulse129 lags the trailing edge of the pulse 126 by a time interval equal toty-tg.

As discussed above, a complete address consists of an addressrecognition code, which is common to all receivers, followed by anaddress code which is unique to a given receiver. The addressrecognition code, which is transmitted first, is generated from a presetcondition of shift register of FIG. 1. For purposes of discussion assumethat this preset condition consists of the binary bits 1, 0, l in thethree stages of shift register 100. Such an initial condition is setinto shift register 100 when switch 114 is closed. The closure of switch114 energizes circuit means within block 117 to close the threearmatures (such as armature 134) of ganged momentary call switch 250 ontheir associated contacts (such as contact 135). Call storage switch 119also contains three armatures connected respectively to the threecontacts of momentary call switch 250. The three armatures of storageswitch 119, such as armature 136, can be preset to either make with aground terminal, or the positive terminal of battery 130. Thus, inessence, call storage switch 119 consists of three single pole, doublethrow switches with a choice of making contact between ground potentialor the positive potential of battery 130 with the movable arm of eachswitch. If the movable arm is connected to ground, a logic 0 isrepresented thereby. If the arm is connected to the battery 130, a logic1 is represented thereby. Then when switch 250 is closed momentarily,the logic ls and Os are passed through OR gates 123, 124, and 125 intoshift register 100 to set the stages as shown in FIG. 1.

The address recognition code will thus be generated as shown in theright-hand column of the top row of FIG. 2. Specifically, this addressrecognition code is 1100101, which code is fed into the 7-bit shiftregister 140. An AND gate 141 has seven inputs thereto from the sevenindividual stages of shift register 140, and when the addressrecognition code is present in said shift register, will produce anoutput signal on lead 142 which will energize the control circuit meanswithin block 120. Energization of the block will function to momentarilyclose the three movable arms of momentary call switch 121, which willreset the three stages of shift register 100 in accordance with the codewhich has been preset in call storage switch 122.

It will be noted that the code present in call storage switch 122represents the initial settings required to generate the unique addresscode of the receiver being addressed.

The shift register 100 then proceeds to generate the address code inaccordance with its present condition wh itlioin the particular exampleshown in block 122 is In FIG. 2 there is shown a chart illustrating thesignals generated by the shift register generator 100 of FIG. 1 for anygiven initial setting of the three stages of shift reg1ster 100. Forexample, if shift register 100 initially contains the bits 101, then theoutput signal supplied to the modulating means 111 from shift register100 will be as shown in horizontal row 1 of FIG. 2; and specificallywill consist of bits 1100101, with the bit at the right occurring firstin time and the others following in sequential order.

The vertical column (labeled Initial Setting) of 3-bit codes representsthe seven possible combinations of such 3-bit codes, excluding 000. Eachof these 3-bit codes will produce a different 7-bit character and isused as the initial setting of the various code generators to producethe different address codes. The column of 3-bit codes is arranged suchthat succeeding codes represent the condition of the code generatorafter the generation of a single bit. Thus, if the register 100initially contains the bits 101, the said three stages for the shiftregister will contain the bits 010 after the first shift signal, andwill contain the bits 001 after the second signal pulse, and willcontain the bits 100 after the third shift pulse, and so on throughseven different configurations. The eighth 3-bit code is the same as thefirst in the left-hand column of FIG. 2 and represents the completion ofthe cycle. Repetition of the first seven will occur beginning with theeighth 3-bit code. There are only seven different combinations possiblewith the three stage shift register since the code setting 000 is notallowable, or even possible. in this particular arrangement. There mustalways be at least one mark or 1 contained in the register in order forthe system to generate a new code.

In the right-hand vertical column of FIG. 2 are shown eight groups of7-bit code characters. Each of these 7-bit words, or characters,represent the first seven hits generated by the particular setting ofthe three stages of the shift register 100 of FIG. 1; said particularsetting being shown in the corresponding row of the left-hand column ofFIG. 2. For example, as stated above, if the three stages of theregister 100 contain bits 101, then the first seven bits supplied fromstage 103 to modulating means 111 are as shown in the first row of theright-hand column of FIG. 2, and consist of bits 1100101, with theright-hand bit occurring first in time. If the generation of the bitscontinues, the said seven bits will be repeated over and over again.

Similarly, if the condition of the three stages of the register 100contain bits 010, then the first seven bits generated therefrom are1110010, as shown in the second row of the right-hand column of FIG. 2.In a like manner, the remaining five 7-bit codes are generated as aresult of various bit settings of the three stages of shift register100, as indicated in the left-hand column of FIG. 2.

It will be observed that each of the 7-bit codes in the right-handcolumn of FIG. 2 follow the same sequence, except that each begins at adifferent point in the cycle of seven bits. More specifically, each ofthe 7-bit codes lag the 7-bit code immediately above it by one bit.Thus, the code in row 2 would be the same as the 7-bit code of row 1, ifthe 1 at the left-hand end thereof were placed at the right-hand endthereof.

Referring now to FIG. 3, there is shown a block diagram of the receiverportion of the station. Such. receiver portion is constructed to receiveand identify the address (redundant) code generated by some transmitterin the system. It is to be understood that the structure of FIG. 3 doesnot show any structure for decoding intelligencebearing information;FIG. 3 shows only that structure necessary to receive and identifyaddress codes.

The redundant code (address recognition code plus address code) from thetransmitter, followed by data, is received and intercepted by antenna10, and then demodulated in receiver demodulator 11 to remove thecarrier and leave only the pulses representing marks and spaces. Areceiver synchronizing timing source 18, which may be responsive to thereceived signal through lead 140, functions to generate a synchronizingsignal of frequency f which is the bit rate of the generated redundantcodes. The synchronizing timing source 18 is further constructed toproduce two output pulse trains which are phased apart in accordancewith the curves A and D of FIG. 4. The pulse train of FIG. 4D representsthe shift pulses employed to shift the shift registers 14 and 36 of FIG.3, and the pulse train of FIG. 4A represents sampling pulses employed togate information into the shift register 14, to reset counters 30 and51, and to reset shift register 36, as will be discussed in detaillater. The waveforms of FIGS. 4E and 4F represent the signals employedto compare the information received and stored in shift register 14 withthe redundant code which is generated locally in generator 93, whichcontains shift register 36.

As discussed briefly hereinbefore, the general concept of the receiveris as follows. The received data is stored in the 7-bit shift register14 in a serial manner and, of course, will change as each new bit isreceived from the transmitter. When the address recognition code isfully entered into the shift register 14, detection thereof will be madeby AND gate 76. Following such detection, which will occur in allreceivers, each receiver will generate its own local address code whichwill then be compared with the received address code to be entered intothe shift register immediately following the address recognition code.

The flip-flop 77, the AND gate 78, and counter function to respond to anoutput from AND gate 76 to open AND gate 82 and thereby reset counter30. Resetting of counter 30 operates to initiate the comparison functionof the receiver; that is, the comparison of the received address codestored in the shift register 14 with the local address code generated bygenerator 93.

Both the generation of the local address code and the recirculation ofthe information in shift register 14 is controlled by the output ofcounter 30, which counts from 0 to 7. Means, including a constantlyproducing high rate pulse source 26 and AND gate 28, which has acountof-7 feedback input 149 from counter 30, functions to supply asingle group of 7 pulses to counter 30 after the reception of an addressrecognition code. The output of the counter 30 is supplied to shiftregister 14 through delay means 32 and OR gate 23 and to the input ofthe local code generator 93 through delay means 32. The said delay means32 functions to permit complete entry of a newly received bit into shiftregister 14 before recirculation of the information in register 14begins. AND gate 48 and bit error counter 51 function as a comparisoncircuit to determine if sulficient coincidence exists between thelocally generated address code and the code stored in the 7-bit register14 to reasonably insure that the proper address has been obtained.

When sufficient coincidence exists between the bits stored in shiftregister 14 and the output of generator 93, counter 51 will count to asufficiently high value to open AND gate 56 so that upon the occurrenceof the next shift pulse the single input bistable device 57 will be set.

As the result of the set condition of bistable device 57,

output AND gate 15 is opened to permit passage of subsequently receivedinformation data through lead 17 to other portions of the receiver, notshown in FIG. 3.

The operation of the circuit of FIG. 3 will now be discussed in detail.A bit pulse, such as pulse 143 of FIG. 4B, is supplied from demodulator11 of FIG. 3 to an input of AND gate 12. Such pulse begins at time t andterminates at time t which constitutes a bit length. At time t asampling pulse 144, shown in FIG. 4A, is generated by timing source 18and supplied to the other input 60 of AND gate 12, causing a sampledportion of FIG. 40 from input bit 143 of FIG. 43 to be supplied to input24 of shift register 14 through OR gate 13.

It should be noted that just prior to the reception of the bit 143, ashift pulse 146, shown in FIG. 4D, was supplied from timing source 18through OR gate 23 to shift register 14 to cause the contents of each ofthe seven stages therein to be advanced one stage, thus leaving thefirst stage open for the reception of the sampled bit 145 of FIG. 4C.

Until the receiver has been addressed, the data bits shifted out of thelast stage of shift register 14 are not utilized in any manner sinceboth AND gates 154 and 15 are closed, i.e., are not yet conductive.

Assume, however, that an address recognition code 1100101 is enteredinto the seven stages of shift register 14. Assume, further, that theentering of the address recognition code into shift registed .14 iscompleted with the sampling 145 of FIG. 4C which occurs at time 1 TheAND gate 76 will now have an output signal which will set flip-flop 77,which will in turn prepare AND gate 78 to conduct shift pulses tocounter 80 when they are supplied via lead 79.

Such shift pulses will pass through gate 78 and cause counter 80 tocount to 7. At the count of 7, a pulse will be supplied from counter 80through lead 81 to AND gate 82, to prepare said AND gate for opening. InFIG. 4D assume that shift pulse 168 is the seventh shift pulse to besupplied to counter 80 to cause opening of AND gate 82.

The following sampling pulse 162 of FIG. 4A will then pass through ANDgate 82 and reset counter 30 to 0. The pulses from pulse source 26 willpass through gate 28 and cause counter 30 to count to seven and togenerate seven output pulses (pulses 166 in FIG. 4B) on output lead 31thereof. At the count of seven AND gate 28 will become inhibited byvirtue of the feedback lead 149 from counter 30 to inhibit terminal 29of AND gate 28. AND gate 28 will now be closed, i.e., nonconductive,until counter 36 is again reset to by the reception of another addressrecognition code in the manner described above.

It should be noted that the output of high pulse rate source 26 has afrequency sufficiently great to permit the seven comparing pulses tooccur between the trailing edge of a sampling pulse, such as pulse 162of FIG. 4A, and the leading edge of the next shift pulse, such as pulse165 of FIG. 4D.

As indicated above, the seven pulses generated by counter and suppliedfrom delay means 32 perform two functions. Firstly, the seven pulsesoperate to recirculate the seven data bits stored in shift register 14through two paths. One of these paths is from the output of the shiftregister 14 through lead 151 to input of AND gate 48. The other path isthrough lead 152 to input 153 of AND gate 154. The latter path is therecirculating path and simply restores into the shift register theinformation which has been shifted out of the end stage thereof.

The AND gate 154 is caused to become open to permit recirculation duringthe time interval A-t (FIG. 4F). The opening time t, is established bythe simultaneous occurrence of count 7 of counter 89 and the laggingedge of an F1 sampling pulse. AND gate 90 is responsive to said twoconditions to set flip-flop 91. The setting of flipfiop 91 prepares ANDgate 154 for opening through lead 92. At time r the shift pulse 165functions to reset fiipfiop 91, thus closing AND gate 154.

The other function of counts 17 supplied from delay means 32 is toenergize shift register 36 to generate a redundant code therefrom. Theseven counts from delay means 32 are supplied to shift register 36 vialead 35 and perform a shifting function. As described in connection withFIG. 1, the shift register 36 in cooperation with feedback meansincluding leads 70 and 71, exclusive OR gate 40, and feedback lead 34function to generate the redundant code on output lead 47. Suchredundant code is supplied to input lead 49 of AND gate 48.

Thus, the information stored in the shift register 14 and the redundantcode generated by shift register 36 are supplied simultaneously to ANDgate 48. If coincidence occurs between enough of the pairs of bits asthey are presented to AND gate 48, an output signal appears on outputlead 156 of AND gate 48. Such output pulse is supplied to bit errorcounter 51, the output lead 53 of which is connected to input lead 54 ofAND gate 56. When sutiicient coincidence exists between the informationin register 14 and that generated by generator 93, the coincidencecounter 51 will count to its maximum count of 6, indicating suchsufficient coincidence and insuring, within desired tolerance, that .theaddress stored in the shift register 14 and that generated by thegenerator 93 are the same. The maximum number of coincidences in theparticular embodiment of FIG. 3 may be seven, since seven hits are beingcompared. However, assume that a tolerance of one error is permitted,within which tolerance the address can be assumed to be correct. Itshould be noted that the actual maximum capacity of the counter 51 issix, so that it will register a count of six Whether the count isactually six or seven.

When counter 51 does contain a count of six, there will appear on thecount-of-six output lead 53 a signal which is supplied to input lead 54of gate 56. Then, when the next subsequent shift pulse occurs and issupplied to input lead 55 of AND gate 56, the single input bistabledevice 57 will be changed from its reset state to its set state. Theoutput gate 57 is responsive to the set state of bistable device 57 topass data. It is to be noted that two conditions are necessary to passdata to output terminal 17. Firstly, the bistable device 57 must be inits set condition and, secondly, a shift pulse must be present on inputlead 160 of AND gate 15. Thus, the comparison circuit 159 is employedboth to open out-put gate 15 and to close said output gate. Morespecifically, if output gate 15 is initially closed, the reception ofthe proper address signal will result in the bistable device 57 beingset so that output gate 15 will pass information supplied to its inputonto output terminal 160. When the next address code (at the end of themessage) is delivered, coincidence counter 51 will again count to itsfull count of 6 and, upon reception of the following shift pulse fromtiming source 18, the bistable device 57 will assume its reset state,thus closing output gate 15 and preventing passage of more datatherethrough.

It is to be noted that in the absence of sufficient 00- incidencebetween the information stored in shift register 14 and the redundantcode generated by generator 93, the coincidence counter 51 will notreach a count of 6 and the bistable device, consequently, will not beenergized. The coincidence counter 51 is reset to zero once during eachbit interval by a sampling pulse (of FIG. 4A) supplied thereto throughlead 52 from timing source 18.

As discussed 'hereinbefore, the address codes can be transmitted inparallel form as well as serial form. In FIG. 6 there is shown amodification of the transmitter adapted to transmit the signal inparallel form. When transmitting in parallel form, it is not necessarythat an address recognition code precede the address code since there isno danger of the bits of one code overlapping and becoming a part of theaddress code. In FIG. 6 the address code is generated by closing startswitch 114' which, in turn, energizes control circuit 213 to momentarilyclose switch 211. The stages of shift register are then set inaccordance with call storage switch 212 and the generation of theaddress code is initiated by supplying timing pulses from source 115' toshift register 100'. The generation of such address code is in seriesform and is supplied to shift register 20-7 in series form. When theaddress code has been fully entered into shift register 207, the controlcircuit 205 is energized (by counting means 294) to momentarily closethe movable arms of switch 296 onto contacts 214 and thus transmit theaddress code in parallel form through said movable arms. After passageof one bit time interval the movable arms are returned to their normalposition; which normal position is to make with the contacts connectedto the message source 208.

The counter 204 functions to respond to input pulses from pulse source115, after starting switch 114 has been closed, to count the number ofpulses supplied toshift register 100. At the count of 7 there will havebeen generated and passed into shift register 2137, seven bits, whichbits constitute the address code. Such address code is then ready to betransmitted.

Referring now to FIG. 7, there is shown a form of the receiver adaptedto receive codes transmitted in parallel form. The structure of FIG. 7is similar to that of FIG. 3 in many respects, and components of FIG. 7which correspond to components of FIG. 3 have the same referencecharacters, although primed.

In FIG. 7 the code is received in parallel form by de modulator and isthen supplied through AND gates 182 to the seven stages of shiftregister 183 in parallel form. As in the case of the structure of FIG.3, the received input is sampled and by sampling pulses, as shown inFIG. 8A. For example, sample pulse samples the received data shown inFIG. 8B. It is to be noted that while only one bit is shown in FIG. 8B,actually all seven bits of the received signal are sampled at the sametime since all are being received in parallel.

The shift register 183 is of the type whereby information can either beshifted from stage to stage in the conventional manner, or in whichinformation can be transferred out therefrom in parallel. The shifttiming signals shown in FIG. 8D function to shift the information out ofthe shift register in such parallel form via leads 195 and to the outputgates 260 through 266. On the other hand, the counter output pulses 194of FIG. 8E function to shift the information in the shift register 183from stage to stage and means are provided to recirculate theinformation back into the input stage as it is shifted out of the outputstage.

Each sampling pulse, which samples the incoming code and enters it intoshift register 183, also resets counter 30 to 0 and initiates a count ofseven therein With the aid of high rate pulse source 26' and inhibit ANDgate 28', in the manner described re. FIG. 3. The output of counter 30is supplied through delay means 32' back to the input of shift register183 and also to local code generator 3'. The code stored in shiftregister 183 is recirculated by the seven output pulses supplied theretothrough lead 184. The code stored in register 183 is also supplied inseries to the input lead 50' of AND gate 48'.

Simultaneously, the local code generator 93' generates the local addresscode which is supplied to input lead 49 of AND gate 48 through lead 47.Counter 51', AND gate 56, bistable device 57', and output AND gate 15'then function, in the manner described re. FIG. 3, to open output ANDgates 260 through 266, when sufficient coincidence exists between thereceived code and the locally generated address code.

Upon receipt of another address code at the end of the message, theprocess is repeated except that the bistable device 57 will now becaused to assume its other state and thereby close output gates 269through 266.

In FIG. 9 there is shown a difierent and somewhat simplified structurefor receiving codes transmitted in parallel form. Such codes areintercepted by antenna 215 and supplied to a receiver demodulator 216.The 7-bit code is then supplied in parallel via the seven output leads220 to address-responsive AND gate 213 and also to receiversynchronizing source 217. The AND gate 218 is constructed to respondonly to the address code and will prepare the AND gate 219 forconductivity When such an address code is present.

The receiver synchronizing source 217 responds to the received signal toproduce the synchronizing (sampling) pulses shown in FIG. 10. One ofsaid synchronizing pulse trains is designated as sampling pulse A andthe other is designated as sampling pulse B. Sample pulse B followssample A in time for any given code frame interval and passes a pulsethrough gate 219 when an address code (logic 1) is being received. Theoutput of gate 219' causes single-input bistable device 224 to changestates. Assuming bistable device 224 has been in its set state, such anoutput pulse will cause it to assume its reset state and prepare ANDgate 221 for conductivity. Thus, when sample pulse A occurs at the nextbit interval, the output from AND gate 221 will open AND gates 225through 231 and all subsequently received codes will pass into thereceiver via leads 237, for processing.

When the next address code, marking the end of transmission, isreceived, the bistable device 220 will be caused to assume its setcondition, thus closing gate 221 and preventing the reception of furtherinformation by that particular receiver.

It is to be understood that the forms of the invention shown anddescribed herein are but preferred embodiments thereof and that variouschanges may be made in circuit arrangement and in specific logicemployed without departing from the scope or the spirit of theinvention.

I claim:

1. A selective calling system comprising:

first generating means for generating an address recognition codefollowed by a first redundant address code and receiving means forreceiving said redundant address code,

12 said first generating means comprising:

first shift register means having N stages therein,

and having input terminal means; first exclusive OR gate meansresponsive to the states of preselected stages of said first shiftregister to produce output signals; first means for supplying the outputsignals of said exclusive OR gate means to the input terminal means ofsaid first shift register means; shifting means for shifting theinformation in said first shift register means along consecutive stagesthereof; and first means for presetting the stages of said first shiftregister means to preselected states; said receiving means comprising:

second shift register means constructed to receive and store the addressrecognition code and the redundant address code; second generating meansfor generating a unique redundant code in serial form and having thesame pattern as the received redundant address code; recognition meansresponsive to said address recognition code when it is stored in saidsecond shift register means to produce a recognition signal; thirdsignal generating means responsive to said recognition signal togenerate a burst of pulses after the reception of storage of thereceived redundant address code but before the reception of another bit;said second shift register means and said second generatingmeansresponsive to said burst of pulses to produce at their outputs theredundant address codes stored and generated therein, respectively; andcomparing means for comparing coincidence of the individual data bits ofthe output signals produced by said second shift register means and saidsecond generating means. 2. A selective calling system comprising: firstgenerating means for generating an address recog nition code followed bya redundant address code, and receiving means for receiving saidredundant address code; said receiving means comprising:

second generating means for locally generating said redundant addresscode and comprising:

first shift register means; first exclusive OR gate means; means forsupplying the output of said first exelusive OR gate means to the inputterminal means of said first shift register means; and shifting meansfor shifting the information in said first shift register meanstherealong; second shift register means having M stages and constructedto receive and store the address recognition code and the redundantaddress code generated by said first generating means; recognition meansresponsive to said address recognition code when it is stored in saidsecond shift register means to produce a recognition signal; thirdgenerating means responsive to said recognition signal to generate aseries of impulses M between the occurrence of adjacent data bits; saidfirst shift register means and said second shift register meansresponsive to said series of M pulses to produce at the output terminalsthereof, respectively, the locally generated redundant address code andthe redundant address code and the received re- 13 dundant address codestored in said first shift register means; and means for comparing theindividual bits of said first and second redundant codes to determinethe degree of coincidence therebetween. 3. A selective caliing system inaccordance with claim 2 comprising:

first shifting means for shifting the information stored in said secondshift register means immediately before the reception of a data bit fromsaid first gen erating means; and means for resetting the stages of saidfirst shift register means to predetermined states immediately precedingthe generation of each series of M pulses. 4. A selective calling systemin accordance with claim 3 comprising:

switching means responsive to a predetermined level of coincidencebetween said received and locally generated redundant address codes toprepare said re ceiver means for receiving message data following saidredundant code. 5. Receiving means for receiving and recognizing aspecific code comprising:

first signal generating means for locally generating at said receivermeans said specific code in serial form; first shift register meansconstructed to receive and store the received code; timing means; secondsignal generating means responsive to said timing means to generate aburst of pulses after reception and storage of said received specificcode; said first shift register means and said first signal generatingmeans responsive to said burst of pulses to produce at their outputs thespecific codes stored and generated therein, respectively; and comparingmeans for comparing the coincidence of the individual bits of the outputsignals produced by said first signal generating means; said firstsignal generating means comprising:

second shift register means having input terminal means and N stagescapable of producing a redundant code of M bits; exclusive OR gate meansresponsive to selective stages of said second shift register means tosupply input data to said input terminal means thereof; and meansresponsive to said timing means for setting the stages of said secondshift register means to predetermined states immediately preceding thegeneration of each of said bursts of pulses; said second shift registermeans responsive to said burst of pulses to generate said specific code;shifting means for shifting the information stored in said first shiftregister means immediately before the reception of a data bit from saidfirst signal generating means; and switching means responsive to apredetermined level of coincidence between the output of said firstshift register means and said second shift register means to preparesaid receiver means for receiving message data following said specificcode.

References Cited UNITED STATES PATENTS 3,001,176 9/1961 Ingham 340-1473,064,080 11/1962 Rea et al 178- 23 3,069,657 12/ 1962 Green et al340171 3,114,130 12/1963 Abramson 340146.1 3,141,928 7/1964 Davey et a1.178-50 MALCOLM A. MORRISON, Primary Examiner.

C. E. ATKINSON, Assistant Examiner.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,384,873 May 21, 1968 Roshan Lal Sharma Column 10, line 1, "57" shouldread 15 Signed and sealed this 30th day of December 1969.

' (SEAL) Attest:

Edward M. Fletcher, Jr. WILLIAM E. SCHUYLER,

Attesting Officer Commissioner of Patents

